Subject: MIPS TECHNOLOGIES ANNOUNCES Date: 17 Oct 1994 17:16:21 -0500 Message-ID: <37ut3l$arq@dcdmjw.fnal.gov> [...] By combining dynamic scheduling with non-blocking caches, the R10000 microprocessor gains much of its performance. With dynamic scheduling, the processor can operate at its highest efficiency by reordering instructions to suit the available execution unit resources. The instructions can then be executed and completed out of order and then reordered or "graduated" back in their original order. This dynamic scheduling makes the fullest use of the microprocessor's extensive execution units and keeps them from going idle. Non-blocking caches keep the processor active while waiting for data it may need for a later operation. The four-way superscalar R10000 microprocessor can fetch four instructions and issue up to five instructions per cycle. Furthering its performance, the R10000 processor has five independent fully pipelined, low-latency execution units. To speed data flow the processor supports large register files and features a large on-chip primary cache with 32 kilobytes for instructions and 32 kilobytes for data. The R10000 microprocessor also features an on-chip secondary cache controller for supporting 512 kilobytes to 16 megabytes of synchronous secondary cache. Both the primary and secondary caches are two-way set associative. The innovative MIPS Avalanche bus enables split transactions, the ability for two or more operations to overlap their execution at the same time. The Avalanche bus allows holding up to eight outstanding transactions at one time prior to execution. [...] The R10000 processor has a die size of 297.6 square millimeters and approximately 6 million transistors. It is designed for implementation in 0.5 micron CMOS. The initial partners for the MIPS R10000 microprocessor are NEC Corporation and Toshiba Corporation. Samples are targeted to become available in the first half of 1995. [...]