Other

Processors

MIPS

Beginning in the late 80s SGI built workstations and servers using the MIPS R2000 RISC processor and its successors. The first SGI computer featuring such a microprocessor was the Professional Iris. The following is a short overview of MIPS RISC processors relevant to SGI computer systems.

MIPS R2000
The R2000 processor is based on the Stanford MIPS project (Microprocessor without Interlocking Pipeline Stages) and is thus the first commercial implementation of the design. It was introduced in 1985 by MIPS Computer Systems (other sources say it was shipped 1987). The R2000 is a full 32bit RISC CPU. The floating point unit that goes with this CPU is the R2010.
Wikipedia MIPS R2000
SPIM Documentation on R2000
 
MIPS R3000
The MIPS R3000 processor is a piplined 32bit RISC processor that implements the MIPS I instruction set architecture (ISA). Technically it is a redesign of the R2000 that allows higher clockspeeds. So it shares the features with the earlier model. The R3000 processor pipline has 5 stages. The CPU includes 32 KB instruction and 32 KB data cache for a total of 64 KB on-chip 1st level cache. Floating point capabilities can be added with the R3010 FPU. The processor was introduced approximateley 1988.
Wikipedia MIPS R3000
MIPS R4000
As all R4x00 series processors the R4000 is a 64bit processor and implements the MIPS III instruction set thus making the processor compatible to its predecessors. They contain 32 64bit integer registers and 32 64bit floating point registers, are superpiplined (8 stages) and approach an execution rate of one instruction per cycle. contains an onbaord MMU with a TLB (to provide rapid virtual to physical address translation) and an on-chip R4010 floating point unit. The R4000 contains an 8KB instruction and 8KB data cache for a total of 16KB of on-chip 1st level cache. The R4x00 processors have been available and used in different versions. PC (as in "R4000PC") denotes primary cache only and SC denotes secondary cache. The MC versions contain special support for cache architectures in multiprocessor systems. The variants used in SGI systems include SC and PC versions of the CPU only.
Wikipedia MIPS R4000
MIPS R4000 Microprocessor User's Guide (local copy)
 
MIPS R4400
As all R4x00 series processors the R4400 is a 64bit processor and implements the MIPS III instruction set thus making the processor compatible to its predecessors. They contain 32 64bit integer registers and 32 64bit floating point registers, are superpiplined (8 stages) and approach an execution rate of one instruction per cycle. It also contains an onbaord MMU with a TLB (to provide rapid virtual to physical address translation) and contains an on-chip floating point unit. The R4400 processors contain 16KB of instruction cache and 16KB of data cache for a total of 32KB of on-chip 1st level cache. The R4400 processor can support up to 4MB of off-chip secondary level 2 cache and all of the 1st level and 2nd level cache control logic resides on-chip. Like the R4000 the R4400 CPU is also available with and without second level cache which is again denoted by the "SC" and "PC" suffixes.
Wikipedia MIPS R4000
MIPS R4000 Microprocessor User's Guide (local copy)
R4400 Overview
MIPS R4600
As all R4x00 series processors the R4600 is a 64bit processor and implements the MIPS III instruction set. The R4600s are compatible with the R2000, R3000, and R6000 processors. They contain 32 64bit integer registers and 32 64bit floating point registers, are superpiplined and approach an execution rate of one instruction per cycle. It also contains an onbaord MMU with a TLB (to provide rapid virtual to physical address translation), and contain an on-chip floating point unit. Again the PC suffix denotes primary cache only while the SC suffix denotes that the processor also comes with additional support for secondary cache that is -in this case- implemented using an external cache controller located on the processor module. The PC variant obviously was the choice forcheaper entry level systems.
Wikipedia MIPS R4600
R4600 Product Overview
 
MIPS R5000
As a lot of R4x00 processors the R5000 has been available and used in two different versions. The PC version contains only primary cache and no level 2 cache, while the SC versions are used with 512 KB secondary cache. The implemented instruction set is MIPS IV providing also compatibility to the previous instruction sets. All R5000 processors contain 32 64bit integer registers and 32 64bit floating point registers. It has a 32KB instruction cache and a 32KB data cache for a total of 64KB on-chip 1st level cache. The R5000 is a 2-issue superscalar microprocessor which has two execution units that can operate simultaneously, one for integer operations and one for floating point operations. Even though the R5000 has two execution units, it cannot always retire two instructions per cycle. The R5000's execution units are optimized for single-precision multiply-add operations (common in 3D geometry calculations). Once the five stage pipeline is primed, the R5000 can issue a single-precision multiply-add every cycle. The R5000 can also process an integer or load/store instruction at the same time as a single-precision multiply-add.
Wikipedia MIPS R5000
Byte Magazine May/96: Mips R5000: Fast, Affordable 3-D
R5000 Product Overview
MIPS R5200
 
MIPS R8000
The first superscalar implementation of the MIPS architecture is the R8000 (code name "TFP") that has been introduced in July 1994. The R8000 is a 64bit RISC microprocessor with strong emphasis on floating point performance, that is spcifically designed for supercomputing applications. It implements the MIPS IV instruction set architecture (ISA). One of the remarkable aspects of this processor is that it is implemented using multiple chips. It's architecture makes it a processor that is difficult to develop for, so it was used only for a short period of time and in a limited range of systems.
Wikipedia MIPS R8000
R8000 User Manual
R8000 Microprocessor Chipset
Design of the R8000 Microprocessor
R8000 press release
MIPS R10000
The MIPS R10000 ("T5"), which has been made avaiable in 1995, is the first 4-issue superscalar processor in the MIPS history. As the R8000, which has been released a year before, the R10000 implements the MIPS IV ISA and is a true 64bit processor, but in contrast to the R8000 the R10000 is a single chip processor. It includes 32 KB 1st level data and 32 KB 1st level instruction cache for a total of 64 KB on chip 1st level cache. The processor has 5 functional units that actually process the instruction: 2 integer units, 2 floating point units and 1 load/store unit. The pipeline length depends on the functional unit an instruction must pass. The pipeline length is 5 stages for integer, 6 for load/store and 7 for floating point instructions.
Wikipedia MIPS R10000
MIPS IV Instruction Set
Download MIPS R10000 Microprocessor User Guide, Version 2.0 from techpubs.sgi.com
R10000 Technical Brochure
Byte Magazine Nov/94: T5: Brute Force
R10000 press release
 
MIPS R12000
The architecture of the R12000 processor, that has been introduced in 1998, is very similar to the one used in the R10000 processors.
Wikipedia MIPS R10000
Byte Magazine Jan/98: RISC Fights Back with the Mips R12000
MIPS R14000
Like the R12000 the R14000 CPU is an enhanced version of the R10000 architecture.
Wikipedia MIPS R10000
 
MIPS R16000
Like the R12000 and R14000 the R16000 CPU is an enhanced version of the R10000 architecture.
Wikipedia MIPS R10000
MIPS RM7000
 

Motorola

Although SGI became famous for the MIPS based systems the first SGI computers (IRIS 1000, 2000/hardware/systems/iris3000.html and 3000) were based on microprocessors from the Motorola 68000 family. Later on processors of this family were used in the host interface of graphics options like GTX or VGX.

Motorola 68010
The Motorola 68010 was an upgraded version of the Motorola 68000 microprocessor.
Wikipedia Motorola 68010
CPU-World Motorola 68010 family
Motorola 68020
The Motorola 68020 was the first 32-bit microprocessor from Motorola. It is the successor of the Motorola 68010 processor.
Wikipedia Motorola 68020
CPU-World Motorola 68020 family

Intel

SGI also developed systems based on Intel processors. In fact beginning some time after 2000 the lines based on MIPS processors were dropped in favour for Intel based systems.

  • Intel Pentium II
  • Intel Pentium III
  • Intel Pentium III Xeon
  • Intel Itanium
  • Intel Itanium 2

Other Resources

Input Devices

Aside from the keyboards and mice which are common with most computers for special purposes other devices were used. Best known are the Spaceball 3D input device as well as the Dials and Buttons package. These devices are introduced along with pictures on a seperate page.

Network

  • ATM
  • Ethernet
  • FDDI
  • GSN
  • HiPPI
  • InfiniBand
  • Myrinet
  • NUMALINK
  • SCRAMNET(+)
  • TokenRing

Devices and Storage

Removeable Media Devices

Diskette Type Drives

  • 5.25" SCSI Diskette Drive
  • 3.5" SCSI Diskette Drive
  • 3.5" SCSI Floptical Drive (Insite)

CD Type Drives

  • CD-ROM Drives
  • DVD-ROM Drives
  • CD-Writer
  • DVD-Writer

Tape Drives

  • 9-Track Tape
  • QIC-24 Tape
  • QIC-150 Tape
  • Digital Linear Tape (DLT)
  • Digital Data Storage (DDS) on Digital Audio Tapes (DAT)
  • Exabyte Tape

Interfaces

Device and Storage interfaces.

  • ESDI
  • Fibre Channel
  • Firewire (IEEE-1394)
  • IPI
  • SCSI
  • SMD
  • ST-506

Storage Solutions

Types of Storage Solutions

  • JBOD
  • NAS
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Products

  • DiskStation
  • Challenge S Vault
  • Challenge M Vault (see section in Indigo 2 page)
  • Challenge RAID/Vault
  • Origin Vault
  • Total Performance 900
  • Total Performance 9100
  • Total Performance 9300
  • Total Performance 9400
  • Total Performance 9500
  • Infinite Storage RM610/RM660
  • Infinite Storage 120
  • Infinite Storage 220
  • Infinite Storage 350
  • Infinite Storage 4000
  • Infinite Storage 4500
  • Infinite Storage 6700
  • Infinite Storage 10000

Drivetypes

Drives used with Silicon Graphics systems.

  • Harddisks
  • Optical Media
  • Tapes
  • Other